VLSI Interconnect Performance Optimization and Planning A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY JIANG HU IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY

Under the sustained progress in VLSI technology, interconnect wires become increasingly important to system performance. This thesis presents research work on several aspects of VLSI interconnect performance optimization, namely, single-net performance driven routing, routing in the presence of buffer blockages and bays, performance driven multi-net global routing and interconnect planning. Single net routing is first targeted to improve the performance of multi-pin critical nets where both timing and wire resources are stringent. Buffer insertion and driver sizing are combined separately with non-Hanan optimization, which is a topology optimization technique exploiting Steiner nodes off the Hanan grid, to minimize cost subject to timing constraints. A higher-order AWE model is employed to assure solution quality. In real scenarios, the routing problem must be solved in an environment that prohibits buffer insertion in certain areas (called blockages), and makes banks of buffers, called bays, available in others. The second problem determines a route for a multi-pin net to avoid(seek) buffer blockages(bays) as much as possible without large wiring detours, so that buffers can be inserted to improve interconnect performance. This problem is solved by iteratively ripping up a sub-path of an existing routing tree and reconnecting the subtrees through maze routing. The next part of the thesis considers the problem of simultaneous routing of multiple global nets. Two algorithms are proposed: the first optimizes congestion and delay based on hierarchical bisection and a network flow algorithm, while the second optimizes these objectives and in addition, the